Phase-locked loop
In electronics, a phase-locked loop (PLL) is an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
Phase-locked loops can also be used to demodulate frequency modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency.
An important part of a phase-locked loop is the phase detector. This compares the phase of the local oscillator to that of the reference signal. In an analog PLL the phase detector is a linear multiplier. This generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out.
There are several types of phase detectors used in digital phase-locked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flip-flops to determine which of the two signals has a zero-crossing earlier or more often. This brings the signal in even when it is off frequency.
The equations governing a phase-locked loop are the following:
We can deduce how the PLL reacts to a sinusoidal input signal:
Analog Phase-locked Loop
where
the input to the PLL is , the output of the voltage controlled oscillator (VCO) is , the output of the phase detector is . The input to the loop filter is , the output is . Note that is the sensitivity of the VCO and is expressed in Hz/V.
The output of the phase detector then is:
This can be rewritten into sum and difference components using trigonometric identities:
Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MIL-STD-188.
